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Memory Systems: Cache, DRAM, Disk
출판사 : Elsevier
저 자 : Jacob
ISBN : 9780123797513
발행일 : 2007-09-10
도서종류 : 외국도서
발행언어 : 영어
페이지수 : 900
판매가격 : 59,000원
판매여부 : 재고확인요망
도서사이즈 :
주문수량 : [+]수량을 1개 늘입니다 [-]수량을 1개 줄입니다

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   Memory Systems: Cache, DRAM, Disk 목차
On the Topic of Memory Systems and Their Design
▪ Part I: Cache
Ch. 1. An Overview of Cache Principles
2. Logical Organization
3. Management of Cache Contents
4. Cache Cohenrence
5. Implementation Issues
6. Cache Case Studies
7. Memory Systems Overview
8. DRAM Device: Basic Circuits and Architecture
9. DRAM System Signalling and Timing
10. DRAM Memory System Organization
11. Generic DRAM Memory Access Protocol
12. Evolution of DRAM Devices
13. DRAM Memory Controller
14. Memory System Design Analysis
Part II: Disk
15. Overview of Disks
16. The Physical Layer
17. The Data Layer
18. Performance Issues and Design Tradeoffs
19. Drive Interface
20. Operational Performance Improvement
21. The Cache Layer,
23. Performance Testing
24. Storage Subsystems
25. Advanced Topics
26. Case Study
Part IV: Cross-Cutting Issues
27. The Holistic Design of Memory Hierarchies
28. Analysis of Cost and Performance
29. Power and Energy
30. Reliability
31. Virtual Memory
   도서 상세설명   

Is your memory hierarchy stopping your microprocessor from performing at the high level it should be? Memory Systems: Cache, DRAM, Disk shows you how to resolve this problem.

The book tells you everything you need to know about the logical design and operation, physical design and operation, performance characteristics and resulting design trade-offs, and the energy consumption of modern memory hierarchies. You learn how to to tackle the challenging optimization problems that result from the side-effects that can appear at any point in the entire hierarchy.

As a result you will be able to design and emulate the entire memory hierarchy.

• Understand all levels of the system hierarchy -Xcache, DRAM, and disk.
• Evaluate the system-level effects of all design choices.
• Model performance and energy consumption for each component in the memory hierarchy.

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