Reuse Methodology Manual for System-on-a-Chip Designs, 3/Ed > SoC(System on Chip)

Foreword xiii
Preface to the Third Edition xv
Acknowledgements xvii
Introduction 1
Goals of This Manual 2
Assumptions 3
Definitions 3
Virtual Socket Interface Alliance 4
Design for Reuse: The Challenge 4
Design for Use 5
Design for Reuse 5
The Emerging Business Model for Reuse 6
The System-on-Chip Design Process 9
A Canonical SoC Design 9
System Design Flow 11
Waterfall vs. Spiral 11
Top-Down vs. Bottom-Up 15
Construct by Correction 15
Summary 16
The Specification Problem 17
Specification Requirements 17
Types of Specifications 18
The System Design Process 19
System-Level Design Issues: Rules and Tools 23
The Standard Model 23
Soft IP vs. Hard IP 25
The Role of Full-Custom Design in Reuse 27
Design for Timing Closure: Logic Design Issues 28
Interfaces and Timing Closure 28
Synchronous vs. Asynchronous Design Style 33
Clocking 35
Reset 36
Timing Exceptions and Multicycle Paths 37
Design for Timing Closure: Physical Design Issues 38
Floorplanning 38
Synthesis Strategy and Timing Budgets 39
Hard Macros 39
Clock Distribution 40
Design for Verification: Verification Strategy 40
System Interconnect and On-Chip Buses 42
Basic Interface Issues 43
Tristate vs. Mux Buses 47
Synchronous Design of Buses 47
Summary 47
IP-to-IP Interfaces 48
Design for Bring-Up and Debug: On-Chip Debug Structures 51
Design for Low Power 52
Lowering the Supply Voltage 53
Reducing Capacitance and Switching Activity 54
Sizing and Other Synthesis Techniques 56
Summary 57
Design for Test: Manufacturing Test Strategies 57
System-Level Test Issues 57
Memory Test 58
Microprocessor Test 58
Other Macros 59
Logic BIST 59
Prerequisites for Reuse 60
Libraries 60
Physical Design Rules 61
The Macro Design Process 63
Overview of IP Design 63
Characteristics of Good IP 64
Implementation and Verification IP 65
Overview of Design Process 67
Key Features 68
Planning and Specification 69
Functional Specification 69
Verification Specification 71
Packaging Specification 71
Development Plan 71
High-Level Models as Executable Specifications 72
Macro Design and Verification 73
Summary 77
Soft Macro Productization 78
Productization Process 78
Activities and Tools 78
RTL Coding Guidelines 81
Overview of the Coding Guidelines 81
Basic Coding Practices 82
General Naming Conventions 82
Naming Conventions for VITAL Support 84
State Variable Names 85
Include Informational Headers in Source Files 85
Use Comments 87
Keep Commands on Separate Lines 87
Line Length 87
Indentation 88
Do Not Use HDL Reserved Words 89
Port Ordering 89
Port Maps and Generic Maps 92
VHDL Entity, Architecture, and Configuration Sections 93
Use Functions 93
Use Loops and Arrays 94
Use Meaningful Labels 96
Coding for Portability 97
Use Only IEEE Standard Types (VHDL) 97
Do Not Use Hard-Coded Numeric Values 98
Packages (VHDL) 98
Constant Definition Files (Verilog) 98
Avoid Embedding Synthesis Commands 99
Use Technology-Independent Libraries 99
Coding For Translation 100
Guidelines for Clocks and Resets 101
Avoid Mixed Clock Edges 102
Avoid Clock Buffers 103
Avoid Gated Clocks 103
Avoid Internally Generated Clocks 104
Gated Clocks and Low-Power Designs 105
Avoid Internally Generated Resets 106
Reset Logic Function 107
Single-Bit Synchronizers 108
Multiple-Bit Synchronizers 108
Coding for Synthesis 108
Infer Registers 109
Avoid Latches 110
If you must use a latch 113
Avoid Combinational Feedback 113
Specify Complete Sensitivity Lists 114
Blocking and Nonblocking Assignments (Verilog) 117
Signal vs. Variable Assignments (VHDL) 119
Case Statements vs. if-then-else Statements 120
Coding Sequential Logic 122
Coding Critical Signals 124
Avoid Delay Times 124
Avoid full_case and parallel_case Pragmas 124
Partitioning for Synthesis 125
Register All Outputs 125
Locate Related Combinational Logic in a Single Module 126
Separate Modules That Have Different Design Goals 127
Asynchronous Logic 128
Arithmetic Operators: Merging Resources 128
Partitioning for Synthesis Runtime 130
Avoid Timing Exceptions 130
Eliminate Glue Logic at the Top Level 133
Chip-Level Partitioning 134
Designing with Memories 135
Code Profiling 136
Macro Synthesis Guidelines 137
Overview of the Synthesis Problem 137
Macro Synthesis Strategy 138
Macro Timing Constraints 139
Subblock Timing Constraints 139
Synthesis in the Design Process 140
Subblock Synthesis Process 141
Macro Synthesis Process 141
Wire Load Models 142
Preserve Clock and Reset Networks 142
Code Checking Before Synthesis 143
Code Checking After Synthesis 143
Physical Synthesis 144
Classical Synthesis 144
Physical Synthesis 145
Physical Synthesis Deliverables 145
RAM and Datapath Generators 145
Memory Design 146
RAM Generator Flow 147
Datapath Design 148
Coding Guidelines for Synthesis Scripts 150
Macro Verification Guidelines 153
Overview of Macro Verification 153
Verification Plan 154
Verification Strategy 155
Inspection as Verification 159
Adversarial Testing 160
Testbench Design 161
Transaction-Based Verification 161
Component-Based Verification 163
Automated Response Checking 165
Verification Suite Design 166
Design of Verification Components 169
Bus Functional Models 169
Monitors 171
Device Models 171
Verification Component Usage 172
Getting to 100% 172
Functional and Code Coverage 172
Prototyping 172
Limited Production 173
Property Checking 173
Code Coverage Analysis 174
Timing Verification 177
Developing Hard Macros 179
Overview 179
Why and When to Use Hard Macros 180
Design Process for Hard vs. Soft Macros 181
Design Issues for Hard Macros 181
Full-Custom Design 181
Interface Design 182
Design For Test 183
Clock 184
Aspect Ratio 185
Porosity 186
Pin Placement and Layout 187
Power Distribution 187
Antenna Checking 188
The Hard Macro Design Process 190
Productization of Hard Macros 190
Physical Design 190
Verification 193
Model Development for Hard Macros 194
Functional Models 194
Timing Models 199
Power Models 200
Test Models 201
Physical Models 204
Porting Hard Macros 204
Macro Deployment: Packaging for Reuse 207
Delivering the Complete Product 207
Soft Macro Deliverables 208
Hard Macro Deliverables 210
Software 212
The Design Archive 213
Contents of the User Guide 214
System Integration with Reusable Macros 217
Integration Overview 217
Integrating Macros into an SoC Design 218
Problems in Integrating IP 218
Strategies for Managing Interfacing Issues 219
Interfacing Hard Macros to the Rest of the Design 220
Selecting IP 221
Hard Macro Selection 221
Soft Macro Selection 221
Soft Macro Installation 222
Soft Macro Configuration 223
Synthesis of Soft Macros 223
Integrating Memories 223
Physical Design 224
Design Planning and Synthesis 226
Physical Placement 230
Timing Closure 234
Verifying the Physical Design 237
Summary 238
System-Level Verification Issues 239
The Importance of Verification 239
The Verification Strategy 240
Interface Verification 241
Transaction Verification 241
Data or Behavioral Verification 242
Standardized Interfaces 244
Functional Verification 244
Random Testing 247
Application-Based Verification 249
Software-Driven Application Testbench 250
Rapid Prototyping for Testing 251
Gate-Level Verification 253
Sign-Off Simulation 253
Formal Verification 254
Gate-Level Simulation with Full Timing 255
Specialized Hardware for System Verification 256
Accelerated Verification Overview 258
RTL Acceleration 259
Software Driven Verification 260
Traditional In-Circuit Verification 260
Design Guidelines for Emulation 261
Testbenches for Emulation 261
Data and Project Management 265
Data Management 265
Revision Control Systems 265
Bug Tracking 267
Regression Testing 267
Managing Multiple Sites 267
Archiving 268
Project Management 269
Development Process 269
Functional Specification 269
Project Plan 270
Implementing Reuse-Based SoC Designs 271
Alcatel 272
Atmel 274
Infineon Technologies 276
LSI Logic 278
Philips Semiconductor 280
STMicroelectronics 282
Conclusion 284
Bibliography 285
Index 287